IBM confirms fabrication of 7-nm test chip with EUV

July 9, 2015

Albany, NY. An alliance led by IBM Research today announced that it has produced the semiconductor industry’s first 7-nm node test chips with functioning transistors (confirming an earlier report). The breakthrough, accomplished in partnership with GlobalFoundries and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE), could result in the ability to place more than 20 billion transistors on the fingernail-sized chips that power everything from smartphones to spacecraft.

To achieve the higher performance, lower power and scaling benefits promised by 7-nm technology, researchers had to bypass conventional semiconductor manufacturing approaches. Among the novel processes and techniques pioneered by the IBM Research alliance were a number of industry-first innovations, most notably Silicon Germanium (SiGe) channel transistors and Extreme Ultraviolet (EUV) lithography integration at multiple levels.

Industry experts consider 7-nm technology crucial to meeting the anticipated demands of future cloud computing and big data systems, cognitive computing, mobile products, and other emerging technologies. Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), this accomplishment was made possible through a unique public-private partnership with New York State and joint development alliance with GlobalFoundries, Samsung, and equipment suppliers. The team is based at SUNY Poly’s NanoTech Complex in Albany.

“For business and society to get the most out of tomorrow’s computers and devices, scaling to 7 nm and beyond is essential,” said Arvind Krishna, senior vice president and director of IBM Research. “That’s why IBM has remained committed to an aggressive basic research agenda that continually pushes the limits of semiconductor technology. Working with our partners, this milestone builds on decades of research that has set the pace for the microelectronics industry, and positions us to advance our leadership for years to come.”

Microprocessors utilizing 22-nm and 14-nm technology power today’s servers, cloud data centers and mobile devices, and 10-nm technology is well on the way to becoming a mature technology. The IBM Research-led alliance achieved close to 50% area scaling improvements over today’s most advanced technology, introduced SiGe channel material for transistor performance enhancement at 7-nm node geometries, implemented process innovations to stack them below 30-nm pitch, and provided full integration of EUV lithography at multiple levels. These techniques and scaling could result in at least a 50% power/performance improvement for next-generation mainframe and POWER systems that will power the big data, cloud, and mobile era.

“Governor Andrew Cuomo’s trailblazing public-private partnership model is catalyzing historic innovation and advancement. Today’s announcement is just one example of our collaboration with IBM, which furthers New York State’s global leadership in developing next generation technologies,” said Dr. Michael Liehr, SUNY Poly executive vice president of innovation and technology and vice president of research.  “Enabling the first 7-nm node transistors is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities.”

“Today’s announcement marks the latest achievement in our long history of collaboration to accelerate development of next-generation technology,” said Gary Patton, CTO and head of worldwide R&D at GlobalFoundries. “Through this joint collaborative program based at the Albany NanoTech Complex, we are able to maintain our focus on technology leadership for our clients and partners by helping to address the development challenges central to producing a smaller, faster, more cost efficient generation of semiconductors.”

The 7-nm node milestone continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, silicon on insulator, strained engineering, multicore microprocessors, immersion lithography, high speed SiGe, high-k gate dielectrics, embedded DRAM, 3D chip stacking, and air gap insulators.

IBM and SUNY Poly have built a highly successful, globally recognized partnership at the multi-billion dollar Albany NanoTech Complex, highlighted by the institution’s Center for Semiconductor Research (CSR), a $500 million program that also includes the world’s leading nanoelectronics companies. The CSR is a long-term, multi-phase, joint R&D cooperative program on future computer chip technology. It continues to provide student scholarships and fellowships at the university to help prepare the next generation of nanotechnology scientists, researchers and engineers.

www.sunycnse.com

www.research.ibm.com

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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