This article is part of TechXchange: RISC V
Lattice Semiconductor is well-known for its FPGAs. Usually, developers add their own firmware, but the company’s new Lattice Automate provides a more complete solution that incorporates artificial intelligence/machine learning (AI/ML) with motor control.
Lattice Automate targets a range of Lattice FPGAs with a framework that includes a soft-core RISC-V processor, a convolutional-neural-network (CNN) accelerator, and motor control along with Ethernet support (Fig. 1). The system can utilize any number of feedback systems like Hall-effect or current sensors. It also can work in a sensorless environment.
Likewise, Lattice Automate is able to control multiple motors using different drive systems. Included are predictive-maintenance models and application code that can be customized and extended. A host-based, GUI-based interface is available for system monitoring and control.
More complex systems require distributed motor control. Lattice’s EtherConnect technology is designed to connect multiple FPGAs using low-overhead Ethernet-style communication (Fig. 2). The connections can be done in a daisy-chain fashion as well as star configurations. The protocol and signaling is essentially the same but allows non-standard interfaces to be employed.
The real-time communication offers a way to synchronize motor control across the network. Protocol stacks are supplied for the RISC-V core. In addition, a conventional Ethernet interface can be included to provide a gateway.
Lattice’s FPGAs implement a hardware root-of-trust that can be taken advantage of by the RISC-V core. In terms of system configuration, Lattice Propel v2.0 allows a developer to combine features at a block level instead of the more precise, though detailed, Lattice Diamond. The latter is used to create blocks for Propel and provide logic-level design capabilities.
Many processor-based motor-control solutions exist, but Lattice’s approach is more efficient. It’s also possible to handle more and varied motors with an FPGA.
The reference design provided as part of Lattice Automate uses a single CNN accelerator per chip. It also supports TensorFlow Lite. Data collection support is in the mix, too.