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Leveraging RISC-V for AI and Machine Learning

Leveraging RISC-V for AI and Machine Learning

In an attempt to achieve the best TFLOPS per watt for machine learning, Esperanto Technologies is adopting RISC-V in its latest processors.

It’s a work in progress, but Esperanto Technologies is looking to use RISC-V technology in artificial-intelligence (AI) and machine-learning (ML) applications. These days, ML, which is a branch of AI, means deep neural networks (DNNs). That, in turn, requires high-performance computing tailored for processing these types of networks.

Esperanto is developing the ET-Maxion and ET-Minion RISC-V processors to address this growing niche, which up to now has been dominated by GPGPUs and custom hardware designs. Also part of the mix is the ET-Graphics core that targets graphics solutions.

The company’s goal is to have the best teraFLOPS per watt using RISC-V for ML. It will do so using RISC-V Domain Specific Extensions (DSEs), including a RISC-V Vector ISA, Tensor instructions, and additional hardware acceleration. One advantage of RISC-V is that it doesn’t use the entire instruction space, making DSEs possible. Of course, one implementation with a DSE may differ from another, so applications would not necessarily be portable unless they were limited to the common RISC-V subset.

Esperanto is aiming for TSMC 7-nm silicon. The ET-Maxion core is initially based on the open-source, Berkeley Out-of-Order (BOOM) RISC-V processor architecture, although Esperanto plans on significant extensions. The company will continue to manage and support the open-source BOOM repository, but the advanced version will be part of the licensable technology.

The ET-Maxion starts with the 64-bit RISC-V RV64GC instruction set. The core has an out-of-order (OOO) pipeline with multiple cache levels and multiprocessor support.

The ET-Minion is designed for energy-efficient and floating-point intensive tasks. It uses a 64-bit RISC-V instruction set with an in-order pipeline and DSEs. The vector extensions are supported by an integrated vector floating-point unit. The Tensor instructions and other enhancements target machine-learning optimizations as well as support for graphics operations. They’re designed to handle multiple threads of execution.

The target system-on-chip (SoC) will include 16 ET-Maxion RISC-V cores with private L1 and L2 caches, 4096 ET-Minion RISC-V cores, plus hardware accelerators. An on-chip network links all processors within a single address space, providing cache-coherent support. It will also have high-bandwidth DRAM interfaces.

These are ambitious goals, but simulations have proven promising in terms of performance and energy efficiency. Esperanto even developed a shader compiler so that the array of RISC-V cores can tackle graphics chores normally handled by a GPGPU.

Having a large array of cores that can run the RISC-V provides a flexible computing platform. Using DSEs allows these to be configured to specific applications spaces while retaining a common programming environment versus more architecture-specific platforms like GPGPUs.

Esperanto has some significant backing from Western Digital, more known for its storage solutions. Western Digital is riding the RISC-V wave, and plans on using processors based on the RISC-V instruction set in its new products.


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