Electronic Design

IC Packages Feel The Squeeze

Packing more IC functionality into smaller form factors stacks the deck against IC makers and foreshadows difficult interconnect challenges.

How much can one package take? As consumer electronics design features scale down to 45-nm and even 32-nm nodes, IC makers are pushed to the limits to shoehorn more functionality into these packages- and lest we not forget the even thornier interconnection issues.

The logical approach is packaging in the Z direction, or 3D IC packaging. In the meantime, IC makers try to satisfy consumer demands with advanced methods for tried-and-true wire-bonding technology while looking ahead at flip-chip and wafer-chip bonding using through-silicon vias (TSVs).

The quest for denser 3D IC packaging spreads across a spectrum of companies. Amkor, IBM, IMEC, Intel, Qimonda AG, Samsung, STATS ChipPAC, Tessera, Texas Instruments, Tezzaron, Xanoptix, Ziptronix, and ZyCube are all investigating 3D IC packages. Some are also sampling 3D ICs using TSV technology.

For instance, Amkor Technology Inc., a provider of advanced semiconductor assembly and test services, and IMEC, a nonprofit nanoelectronics and nanotechnology research center based in Belgium, entered into a two-year collaboration agreement to develop cost-effective 3D integration technology. It will be based on wafer-level processing techniques.

Market research firm Yolé Dévelopment foresees a number of 2D and 3D technologies that will coexist, depending on the required packaging density. The firm also expects TSV technology to dominate future high-density packaging. According to the company, TSV technology first will be used for packaging memories, followed by adding logic and then control devices in the form of ASICs and system-on-a-chip (SoC) ICs.

Stacking continues to be popular, with advances coming at the chip, wafer, and package levels. Two of the hottest packaging trends are the use of package-on-package (PoP) and multichip package (MCP) methods. Chips with lower yields appear to favor PoPs, but those with high density and performance levels favor MCPs. Another percolating area revolves around system- in-package (SiP) technology, where logic and memory devices are manufactured in their own respective processes and then joined together in an SiP package.

Memory technology likely will be the first to fully utilize TSVs on a production basis. Samsung Electronics Co. Ltd. has crafted an all-DRAM stacked-memory package using waferscale- package (WSP) TSVs housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer.

The wafer-level-processed stacked package comprises four 512-Mbit dual-date-rate (DDR2) DRAM chips for 2 Gbits of high-density memory. The DRAMs are stacked and interconnected with TSVs to form a 4-Gbyte dual in-line memory module (DIMM).

In contrast to wire-bonding techniques, this proprietary technology forms laser-cut, micron-sized holes vertically through the silicon and connects the memory circuits directly with copper filling. A proprietary wafer-thinning technique helps eliminate warped die in the low-profile package. Meanwhile, WSP has advanced even further with Tezzaron's FaStack wafer-stacking technology. It allows for the stacking of sensor, signal-conditioning, memory, and processor chips on a thin 3D package (Fig. 1).

Even printed-circuit-board (PCB) technology has gone 3D. Panasonic Electric Works' microscopic integrated processing technology (MIPTEC) makes it possible to form 3D PCBs on an injection-molded substrate using fine-pitch laser patterning. Panasonic claims MIPTEC enables the development of any number of devices that require flexibility, miniaturization, and optical, electrical, and thermal properties.

A common challenge to all 3D packaging is creating the right interconnect technology. Ziptronix's high-yield direct-bondinterconnect (DBI) technology can be implemented in a die-towafer or a wafer-to-wafer format. It supports an interconnect pitch of less than 10 µm with typical interconnect widths of 2 µm and alignment accuracy of 1 µm.

Sematech, a chip-making consortium, believes the interconnect challenge is crucial. It has opened up membership in its 3D interconnect program to suppliers, chip makers, assembly and packaging companies, and other participants. Launched in 2005, the program has been drafted for the International Technology Roadmap for Semiconductors (ITRS). TSVs represent one of the program's focus areas.

Continued on page 2.

Eliminate Wire Bonding?
Many packaging experts consider TSV to be the next step in interconnect technology. In fact, TSV may very well displace wire bonding. Wire bonding is a mature technology easily implemented with existing equipment. However, it doesn't necessarily provide the shortest path lengths between IC die.

Also, wire bonding requires dies with bond pads located at edges. That will ultimately limit the number of connections to the length of the edges divided by the placement resolution of the wire-bonding machine, particularly when using surface-mounting technology (SMT). Wire-bonded stacked chips also need spacing between them, and the wires themselves take up space.

There's no question that wire bonding is an important technology tool, but it may face certain limitations in the future. Wire bonding requires vertical spacing between dies of tens of micrometers, and horizontal spacing of hundreds of micrometers are needed for the die-connecting wires. Moreover, it can be argued that wire bonds introduce potential reliability problems, though the record on this is far from certain.

Still, leading semiconductor IC companies continue to advance the widely used technology, which they believe costs less than TSV technology. Samsung recently used wire bonding to pack 16 NAND die into an MCP module that maxes out at a density of 16 Gbytes. "No one knows how far wire bonding will go," says Dongho Lee, principal engineer for the Interconnect Product and Technology Group at the Samsung Memory Division.

To solve the limitations of wire-bonding bumps, Tessera came up with a micro-contact chip-scale package (CSP) for reduced package pitch in high-density area-array CSP products. The package uses nickel/gold-plated copper bumps that allow for SMT assembling of the CSP to a board. The microcontact bump pad can be reduced to a diameter of only 200 µm, compared with 300 µm for a 0.5-mm pitch ball-grid array (BGA) package (Fig. 2).

Akita Elpida Memory Inc. says it has developed the world's densest MCP module, with 20 stacked die in a package 1.4 mm thick. To achieve such thinness, the company ground down individual dies to 30 nm thick and developed handling equipment for such thin die. Akita then used 40-µm low-loop wire bonding and devised a method to inject resin without disturbing the mechanical assembly.

More and more, flip-chip technology is being used instead of wire bonds. Flip-chip technology connects a die face down to a PCB or a substrate using BGA technology or other conductive bumps. This not only eliminates wire bonds, it also increases signal speeds and reduces overall size constraints.

Freescale Semiconductor took flip-chip technology one step further with its redistributed chip packaging (RCP) approach (Fig. 3). A form of PoP, it delivers a large degree of flexibility thanks to a standardized I/O pin layout. The top chip in an RCP approach can be any ASIC, such as memory, an applications processor, a Bluetooth module, or a camera module.

According to Freescale, RCP offers the best combination of desirable packaging attributes compared to SiP and conventional PoP methods. The company uses RCP technology in its mobile extreme convergence (MXC) platform, which features a single-core modem, a shared-memory subsystem, an RF power amplifier, and power-management functions. As a result, one can opt to put an entire GSM (Groupe Spécial Mobile) EDGE (Enhanced Data rates for GSM Evolution) or 3G radio into a package the size of a U.S. quarter coin.

Tessera's MicroPILR PoP technology could serve a broad array of chip and board applications for mobile consumer devices. It can enable package-to-package connections down to 100 µm and package-to-board links down to 0.3 mm (Fig. 4). Columns stand less than 180 µm high and can be tapered from diameters ranging from 40 to 375 µm. In comparison, solder-ball diameters range from 350 to 500 µm.

Samsung Electronics seeks to develop "true" 3D circuitry through its Fusion program. Described at last December's IEEE International Electron Devices Meeting (IEDM), the program's first device is an ultra-dense NAND flash memory that stacks 32-bit cells in two interconnected layers.

Initial cells are built on a bulk silicon wafer. Then, others are built into a thin SOI-like (silicon-on-insulator) single-crystal silicon layer grown on top of the back-end-of-the-line dielectric with a common source line through the two layers. The common source line solves a potential problem with a floating thin-body SOI structure that allows only one cell at a time to be erased. Samsung believes this SOI approach might be useful for logic circuits, too.

Also this year, STATS ChipPAC announced a stacked flipchip package for mobile telephone platforms. This 3D package combines baseband, memory, and analog functions in a single package-in-a-package (PiP) case.

Continued on page 3

Tsv Times Two
There are two main contending methods of implementing TSVs: conventional dry etching and laser drilling. It's also not clear whether or not it's more cost-effective to generate the TSVs at an IC wafer-fabrication facility or the IC packaging facility. Companies are now examining the suitability of laser systems for drilling a wide variety of substrates, such as ceramics, metal and rare-earth oxides, and polymeric materials of layered composition.

Generally, laser drilling of TSVs is viewed as more costly than conventional dry etching. Yet Jeffrey Albelo, director of the laser singulation group at Electro Scientific Industries, believes laserdrilling costs are lower than those incurred by dry reactive ion etching (DRIE) methods on a normalized cost per 1000 vias. He bases his findings on raw via-drill-rate data.

More companies now see TSVs as the solution to the looming IC interconnect crisis, which, according to the ITRS, could emerge within a couple of years. A semiconductor industry group already has put forth the first draft of a roadmap for TSV technology and hopes to publish it by the end of this year.

IBM announced it will begin sampling the first commercial devices that make use of TSV connections. By next year, the company also will have production quantities of a power amplifier that features up to 100 direct metal links to a power ground plane.

New Materials
IC chip makers have long known that scaling IC geometries downward can crunch the tiny aluminum and copper interconnect wires in IC designs, causing timing delays and other problems. The expected shift to copper interconnects in logic and DRAM circuits will increase unwanted resistivity levels.

Gold is expected to be used more widely for high-density 3D packaging. Kulicke & Soffa Industries recently developed Formax, a new gold wire for stacked and multi-tier applications, that offers consistent loop profiles, linearity, and stability. It's also capable of loop heights of less than 3 to 16 mils with wire spans up to 320 mils in diameter.

Carbon nanotubes (CNTs) may have a future as a material for 3D interconnects. CNTs potentially can carry more current per given area, with current density levels reaching 1 x 107 A/cm2. Fujitsu is developing CNTs for 32-nm designs and demonstrated CNT bundles in 32-nm via holes across 300-mm wafers at approximately 450°C, with resistance values as low as those for tungsten (Fig. 5). The company's researchers are trying to get as close as possible to matching the resistance of CMOS-compatible growth temperatures of 400°C.

Future Routes
How and when 3D packaging developments will evolve depends on a number of factors: How quickly will semiconductor IC manufacturers adopt novel packaging approaches? What cooling methods are needed to dissipate increasing heat levels? What are the compatible processing equipment and tools, and do they have the necessary alignment and accuracy levels?

Most IC experts believe that this may occur over several phases. In all likelihood, flash-memory wafer stacks with TSVs and conductive pastes will evolve. This will be followed by surface-to-surface bonding of ICs with surface bump pitches as small as 5 µm being used. Eventually, a system-on-silicon methodology will evolve in which memory, graphics, and other ICs are bonded face down to the microprocessor chip.

MEMS IC toolmakers are already developing tools suitable for the coming 3D era. Presently used for etching sidewalls and trenches with much larger line widths of hundreds of micrometers, these tools could be adapted for use with finer-line geometries of tens of micrometers typical for 45-nm and 32-nm processing systems.

A number of equipment providers, materials companies, and researchers have joined to create an international organization to address the technical and cost issues involved in creating TSV 3D chip interconnects. The Semiconductor 3D Equipment and Materials Consortium (EMC-3D) will develop processes for creating microvias between 5 and 30 µm on thinned 50- to 300-mm wafers, using both via-first and via-last techniques.

Equipment companies initiating the consortium include Alcatel, EV Group, Semitool, and XSiL. Among the materials companies are Rohm and Haas, Honeywell, Enthone, and AZ. Wafer service support comes from Isonics. Research partners include Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology), and Texas A&M University.

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