As microelectromechanical-systems (MEMS) ICs satisfy more functions and proliferate, packaging them into high-density form factors like 3D becomes more of a challenge than conventional ICs. To suppress costs and make them more competitive in the market, they need high-density packaging. MEMS devices are essentially “machines” that involve motion, not transistors. This means they must be effectively protected from the environments they operate in, which often can be very harsh.
Most MEMS devices are integrated in a package by attaching the MEMS die to a CMOS IC via wire-bonding or by placing the MEMS die above a CMOS silicon wafer. Nevertheless, manufacturing processes that involve 3D MEMS packaging have proven to work by taking advantage of waferlevel packaging (WLP). One such example comes from Innovative Micro Technology (IMT), which successfully made microfluidic and other MEMS functions using through-silicon vias (TSVs).
MEMS ICs need to be packaged in an environment of, say, a vacuum or special gases to keep them clean, allowing them to work properly. “Temperature and other environmental factors are very different from those for conventional ICs,” says John S. Foster, IMT chairman and CEO. Freedom from external mechanical forces is a must, so mechanical isolation is very important.
Many different 3D and WLP approaches are required. Hermetic packaging, which is vital, can involve glass frit bonding, eutectic bonding, gold-gold thermo-compression, and silicon fusion bonding, each of which must be tailored to specific MEMS functions.
Toshiba Corp. came up with an encapsulation technology for moisture-resistant MEMS ICs under normal atmospheric conditions, as opposed to high vacuum levels. This, according to Toshiba, can be used in applications like MEMS packages for mobile phones.
Using chemical vapor deposition (CVD), a hermetic cavity is formed by coating a polymer sacrificial layer with silicon-dioxide (SiO2) film. A cavity is etched on the sacrificial layer through holes in the film, which are covered with a polymer cap. Etching efficiency can be increased by making the film holes larger, but that raises the danger of polymer inflow.
Toshiba says it minimized this problem by using holes of the right size and shape. The company also crafted a corrugated encapsulation structure that increases pressure resistance. Changing the shape of the etching holes from circles to ovals and using a thicker lamination layer makes the process useful for packaging multiple levels of MEMS ICs that require vacuum conditions.
The University of Michigan’s Center for Wireless Integrated Microsystems (WIMS), part of the Department of Electrical Engineering and Computer Science, developed a generic environment- resistant MEMS packaging platform. Known as ePack, it involves packaging individual MEMS devices in a vacuum and allows for temperature control of less than 50 mW and vibration isolation.
Thermal and mechanical isolation are achieved simultaneously using glass isolation suspensions. The suspensions are stiff enough to support the platform and withstand shock and vibration, but also flexible enough to provide thermal and vibration isolation. A thermal impedance of 3000 K/W was achieved, corresponding to power consumption of 43 mW, when the platform is oven-controlled at 85°C and the temperature of the external environment is –50°C.
The thermal isolation can be modified and improved for different MEMS applications. The packaging platform allows for both wafer-level and die-level packaging of MEMS devices. It suits high-performance MEMS gyroscopes, accelerometers, infrared imagers, or any applications requiring low-power temperature control, vibration isolation, and hermetic/vacuum packaging for stable operation.