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Multithreaded Cores Handle Machine-Learning Chores

March 17, 2020
The latest multicore micro from XMOS ups the processing ante by including machine-learning hardware acceleration.

XMOS has built interesting multicore solutions since its inception and the latest xcore.ai is no exception (Fig. 1). At a high level, the xcore.ai looks like previous incarnations. Two physical RISC cores implement eight logical cores that share the performance of the hardware; therefore, it actually makes more sense to view these as eight actual cores.

The large number of cores allows developers to dedicate a core or two to specific functions, including handling real-time hardware chores. Having a core waiting on a hardware event is faster than dealing with interrupts and can simplify the overall software support as well. There are plenty of other cores to handle other chores.

The cores and software support are designed to handle real-time communication between the cores. This is facilitated by the switch that connects everything, including the new vector-processing unit, DSP support, machine-learning support, and cryptographic support. This distribution keeps the RISC cores simple while providing access to the hardware acceleration, which can make the difference in system performance.

The large number of logical cores in the xcore.ai allows applications to become dedicated cores to handle application services (Fig. 2). A typical application might include a neural-network model using three cores while the application operates in a pair of cores running something like FreeRTOS. In this example, four cores handle the far-field microphone and sensor data processing. The FreeRTOS runs as a conventional round-robin operating environment, possibly handling a dozen tasks, while the other cores run their dedicated applications deterministically.

Applications that incorporate machine learning can employ TensorFlow Lite for Microcontroller models on the RISC cores. The dedicated hardware accelerators can be used for models that require heavy lifting.

The chip has 128 I/O pins that can be managed in software for bit banging or peripheral support that would be difficult with a conventional multicore micro. Dedicated hardware interfaces such as USB 2.0 support integrates a built-in PHY and the MIPI interface.

Much of the hardware support is accessible via C libraries, thus simplifying their use. A full development suite with C compilers that can support the hardware are available. FreeRTOS integration is included, too.

Overall, the xcore.ai provides a flexible, real-time, multicore platform that would be hard to beat using a more conventional multicore approach. This is especially true where high-speed, custom interface support is required. Software can run on the xcore.ai in a fashion that meets interface tight timing requirements, unlike an interrupt-based system. Likewise, the hardware communication system between cores enables low-latency communication.

Thanks to the large number of cores, developers can allocate cores based on real-time peripheral support and internal machine-learning model support. This produces a more flexible design environment and enables better allocation of system resources even later in the development process, since the communication subsystem allows tasks to run on any core.

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