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7-nm ASIC Technology Sets Sights on Future Data Centers

Oct. 20, 2020
A wide range of advances in silicon engineering design-based product development have emerged over the past few years. Specifically, ASIC/FPGA-based node design has progressed toward advanced nodes of 7 nm and lower.

What you’ll learn:

  • 7-nm ASIC technology benefits in the semiconductor industry.
  • Role of the 7-nm ASIC advanced node in data centers.
  • Cost trends of advanced nodes in the semiconductor industry.

As more consumers embrace smart devices, demand grows for networking data centers, Internet of Things, smart sensors, etc. To meet these needs, semiconductor design companies are encountering challenges in chip design complexity and PPA (power, performance, area) factors in lower geometries, such as 7 nm, 5 nm, and 3 nm. One of the leading global semiconductor companies, headquartered in Santa Clara, Calif., says “The 7-nm node offers a 20-30% performance improvement, 30% power reduction, and at least a 10-15% die cost reduction.” 

For semiconductor design services, 7-nm ASIC competencies include:

  • Large-scale design partition and signoff benefits
  • Design layout with DFT silicon bring-up
  • 2.5D IC packaging design flow

The above-mentioned capabilities provide plug-and-play silicon design solutions to reduce layer count, which in turn results in lower cost. In the era of miniaturization, 7-nm ASIC technology is having a significant impact throughout product engineering services. Also, the elements of an advanced 7-nm ASIC chip are delivered by many IP integrated and supply-chain providers.

7-nm ASIC Technology: Fueling Next-Gen Data Centers

According to Markets and Markets, the data-center accelerator market was valued at US$1.60 billion in 2017 and is expected to reach US$21.19 billion by 2023—a CAGR of 49.47% during the forecast period (Fig. 1). And that will ramp up the data-center processor (ASIC/FPGA) industry in upcoming years.

Earlier data-center designs look somewhat similar to the latest data centers at the outset, but their inner workings are fundamentally different from each other (Fig. 2). Various types of data centers exist, such as the hyperscale data center, colocation data center, wholesale colocation data center, enterprise data center, and telecom data center, whose size, structure, and format are different. However, they have common groups of interconnected servers. Each server is a high-performance computing (HPC) system with a large storage space, memory, processing power, I/O possibilities, etc.

For certain data centers, the growth of the market for 7-nm ASICs is attributed to the increasing adoption of ASICs for accelerating enterprise workloads in the networking data-center sector. Many data centers use high-bandwidth-memory (HBM) stacks for large storage areas, which is easily accessible by the ASIC. They also use 2.5D IC packaging in stacks, so the physical interface to those stacks become the key element of the power and performance profile for ASICs in the cloud and data centers.

 As requirements of emerging technologies intensify, the demand for improved reliability, real-time visibility, cloud security, AI and ML data workloads, and memory storage across hybrid networking architectures also continues to rise. To address this demand, the semiconductor industry is bringing ASIC design support to the data-center industry with the 7-nm node. It offers wide-ranging semiconductor solutions for wired, wireless, networking, and data-center applications.

A 7-nm ASIC works in power system servers that target hybrid cloud and big data workloads of data centers. With a strong focus on 7-nm die-size optimization and performance, engineers work on improving chip frequency with 40% to 70% chip area utilization, higher throughput, performance, and programmability for next-generation ASIC data centers.

Cost Trends of Advanced 7-nm ASIC Technology for Data Centers

Lower-technology-node design is considered as a notable win for increasingly lower power-consumption and higher performance miniature IoT devices. Major industry players and foundries have already announced their 7-nm chips.

The benefits of 7-nm ASIC technology design can be rewarding in terms of multi-data-center consistency, compatibility, and predictability of data-center networks. These tactics take IP addressing and configuration to a new level in the growing market of AI-driven data centers.

It costs $200 million to design a 7-nm system-on-chip (SoC), which is about nine times the cost of designing a 28-nm device, according to Gartner. “Not that many people can afford to [design chips at 10 nm and 7 nm] unless they have a high-volume runner and can see a return-on-investment,” said Samuel Wang, an analyst with Gartner.

Data centers based on 7-nm ASIC technology typically comprise multi-core, multi-IP, multi-complex algorithms-on-chip that optimize the total cost of ownership (TCO) of large ASICs. But, as mentioned, the main barrier concerns the cost of developing the ASIC, which includes both the mask costs and the ASIC design, which also is much higher compared to earlier processor nodes.

Based on those cost factors, foundry customers who are able to pay for these advanced lower-geometry nodes face some tough decisions when planning to migrate:

  • Where is the 7-nm chip market heading?
  • When considering all aspects of your business, does it make sense to migrate to 7 nm, 5 nm or beyond?
  • Is it a good idea to enter into the emerging technology race, e.g., big data, the mobile industry, and AI/ML?
  • How do you deliver value to the consumer?

The decision-making process ultimately accelerates the right time-to market. There may be cost intricacies in 7 nm, but the return on investment (ROI) over a period of three years can lead to benefits regarding clients looking for a performance edge, meeting the increasing demands of 5G, and the rapid growth of connected devices due to the pandemic.

To address the challenges of data centers—scaling with increasing networking demands and making decisions on the cost factors—silicon engineering companies must manage the design, development, and tape-out of advanced nodes at right time-to-market for their customers.

Komal Chauhan is Senior Marketing Executive and Technical Writer at eInfochips (an Arrow Company).

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