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MCU’s Display Controller Uses Integrated DRAM

June 5, 2017
Microchip’s PIC32MZ family incorporates a display controller that is paired with 32 Mbytes of on-chip DDR2 DRAM.

Microchip’s PIC32 series is based on the 32-bit MIPS core from Imagination Technologies. These microcontrollers have sometimes included display controllers, but the new PIC32MZ family (Fig. 1) incorporates a display controller that can be paired with 32 Mbytes of stacked DDR2 DRAM. This allows it to handle higher-end displays that are typically out of the reach of standard microcontrollers.  The DDR2 controller can also be used with up to 128 Mbytes of off-chip DDR2 DRAM instead of the stacked DRAM.

Stacked DRAM is common on high-end processors typically used in mobile applications, where space is at a premium. They tend to have very large blocks of memory that also support the operating system and applications. The PIC32MZ’s DRAM is designed for display support, with flash and on-chip SRAM being used by the operating system and SRAM.

The 200 MHz microAptiv supports the microMIPS instruction mode that reduces code size by 35%. The core has 32 Kbyte instruction and data caches. It also has enhanced DSP instructions, including a single-cycle MAC with saturating and fractional math support, plus four 64-bit accumulators. The memory management unit (MMU) also supports memory and peripheral protection. The crypto engine supports AES, 3DES, SHA, MD5, and HMAC, and it has a hardware random number generator (RNG).

The graphics controller can drive 24-bit color Super eXtended Graphics Array (SXGA) displays. There is also a 2D graphics processing unit (GPU).

The family supports a range of off-chip memory interfaces, including DDR2 up to DDR2-400, SD/SDIO/eMMC bus interfaces up to 50 MHz, Serial Quad Interface up to 80 MHz, and an external bus interface up to 50 MHz.

The chips use a 4-wire MIPS Enhanced JTAG interface that supports unlimited software and 12 complex breakpoints. There is support for IEEE 1149.2-compatible (JTAG) boundary scan and there is also a built-in non-intrusive hardware-based instruction trace facility.

The chip has a range of digital interfaces including communication interfaces like the dual CAN 2.0B interfaces, SPI/QSPI, I2C, and UARTS. Members of the family include high-speed USB and Ethernet support.

The analog support includes multiple comparators and a six channel, 12-bit ADC that operates at speeds up to 18 Msamples/s. It can handle multiple trigger sources and it can also operate when the chip is in sleep and idle modes. There are also six digital comparators and six digital filters. The chips have an on-chip temperature sensor and a charge time measurement unit (CTMU).

The chip family is supported by Microchip’s MPLAB IDE and Harmony software framework. Pricing starts at $7.73 and chips are available in 169-ball BGA, a 176-pin LQFP, and a 288-ball BGA for external DDR2 support. The PIC32MZ Embedded Graphics with Stacked DRAM Starter Kit (Fig. 2) is priced at $130. External DRAM versions are available, as well.

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