The Crolles2 /Alliance, which includes Freescale Semiconductor, Philips and STMicroelectronics, has created six-transistor SRAM-bit cells with an area of less than 0.25 square microns, or about half the size of earlier solutions, using conventional bulk CMOS technology and 45 nm design rules. The 1.5 Mbit arrays were produced at the alliance's 300 mm wafer fabrication pilot line in Crolles, France.
"We have successfully demonstrated the feasibility of producing functional circuits and ultra-dense SRAM cells at the 45 nm node," said Alliance chief technology officers Claudine Simson, Freescale Semiconductor; Rene Penning de Vries, Philips Semiconductor, and Laurent Bosson, STMicroelectronics.
The Crolles2 wafer fabrication line is currently running pilot production of 90 nm CMOS devices on 300 mm wafers and is on target to prototype 65 nm CMOS during 2005. The alliance executives said their 45 nm achievements “are a vital stepping stone toward future generation high-volume process technologies.”
With each new generation of process technology, engineers have typically reduced area by a factor of two. But as process geometries are reduced and oxide layers get thinner, the control of leakage currents becomes a greater challenge. To meet the challenge, the Crolles2 alliance is evaluating the extension of conventional CMOS process technology to produce SRAM cells at 45 nm while achieving the necessary cell and transistor performance.
Alliance engineers have developed a process that uses existing materials and process flows, maximizing the re-use of technology modules. Scientists at Crolles also are evaluating other solutions, including metal-gate technology and the use of high-k dielectric, which are technically more complex and less mature than standard CMOS logic processes.
