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The Automotive Space Gears Up to Take on RISC-V

Sept. 26, 2022
SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first automotive family cores will become available later this year.

This article is part of the TechXchangeRISC-V: The Instruction-Set Alternative

What you'll learn:

  • How will RISC-V facilitating automotive SoC design, especially for mixed-criticality apps?
  • The lineup of compute IP being developed by SiFive.

Key trends in automotive electronic architecture these days include centralization of computing, increased computing at the sensing edge, higher software complexity due to mixed criticality (a system containing computer hardware and software that can execute several applications of different criticality, such as safety critical and non-safety critical), and a shift from domain to zonal controllers, to list but a few. These requirements have created the need for new, more capable electronic control units (ECUs), and a higher degree of functional integration in fewer devices.

An open standard is one obvious answer, allowing multiple vendors to be used. It helps drive costs down and enables designers to accommodate new capabilities as they become available.

SiFive, an organization that’s not a chip manufacturer but makes the plans for chipmakers to use, employs a RISC-V instruction set architecture (ISA)—a base for building chips that defines what kind of software can run on the chips. Arm Ltd.'s Arm ISA and Intel's x86 are the dominant ISAs used today for general-purpose processors, but both are proprietary while RISC-V is an open standard.

The global RISC-V ecosystem is growing rapidly and now consists of more than 3,000 members. Working without proprietary lock-in, companies can license from multiple vendors and have more flexibility to design their own IP where needed, while maintaining software and ecosystem compatibility.  

Renesas, for example, “has been closely collaborating with SiFive to bring the strong benefits of RISC-V to many of our products,” said Takeshi Kataoka, Senior Vice President and General Manager of the Automotive Solution Business Unit at Renesas. “RISC-V continues to gain momentum around the world, and we plan to leverage SiFive’s portfolio of automotive RISC-V products in our future automotive SoC solutions to meet the exacting demands of these global customers.”

Automotive Compute IP

SiFive is creating a complete lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first automotive family cores will be available later in 2022. And by the second half of 2023, two more product series will be added.

Using a single ISA across its product offerings—from safety islands to real-time products to ADAS and central zone compute—increases code portability and can reduce cost and time-to-market. RISC-V vector extensions will bring enhanced machine-learning and DSP capabilities.

An increasingly important trend in the design of real-time and embedded systems is the integration of components with different levels of criticality onto a common hardware platform. Criticality is a designation of the level of assurance against failure needed for a system component. A mixed-criticality system is one that has two or more distinct levels (for example safety critical, mission critical, and low-critical) like ASIL B, ASIL D, or mixed criticalities with split-lock, which is high compute performance coupled with high safety-integrity support.

SiFive solutions are being developed to address automotive needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification. This is as the automotive market transitions to zonal architectures and manufacturers ask for energy efficiency, simplicity, security, and software flexibility. The RISC-V ecosystem enables a workload-targeted chip design, based on an open specification base that enables industry-wide collaboration to build standards and specifications for commercial competition.

The New Set of Chip Series

SiFive has launched a new product portfolio and its first three automotive product series, each with area- and performance-optimized variants. The company says it’s the only RISC-V IP supplier to offer multiple processor series that meets automotive designers’ needs with regard to compute, integrity, and security.

These latest chips include the E6-A series for digital control applications like steering, S7-A for so-called "safety islands" that act as a failsafe for other critical applications, and X280-A to manage data from image sensors and do machine-learning work, including for autonomous driving.


The automotive E6-A series has IP options that are both area- and performance-optimized for different integrity levels such as ASIL B, ASIL D, or split-lock, in line with ISO 26262. With “split-lock” capability, high compute performance can be coupled with high safety-integrity support.

Split-lock differs from lock-step by adding the flexibility not available in lock-stepped CPU implementations. It allows the system to be configured either in a “split mode” (two independent CPUs that can be used for diverse tasks and applications), or “lock mode” (the CPUs are lock-stepped for high safety-integrity applications) at boot up.

SiFive’s automotive products are accompanied by complete safety packages that include documentation to accelerate Safety Element out of Context (SEooC) integration and, with it, time-to-market. In the automotive world, the SEooC defined in ISO 26262-10 is the method for using components in a vehicle that weren’t originally designed for that specific project. Components that are developed without any idea of where they will be fitted fall under the purview of SEooC.

The E6-A series targets a variety of real-time, 32-bit applications from system control to hardware security modules and safety islands, and as standalone in microcontrollers. E6-A has a 32-bit real-time core and is the first commercially available offering from SiFive with broad availability later in 2022.

Building on the foundations of the SiFive Essential portfolio, the multicore-capable design of the E6-A series offers what’s claimed to be the industry’s best-in-class functional-safety support as a SEooC to enable use in applications with Automotive Safety Integrity Levels (as per ISO 26262) up to ASIL B and ASIL D. The automotive products are accompanied by complete safety packages that include documentation to accelerate SEooC integration.   

E6-AB, targeted at ASIL B integrity levels, employs minimal hardware redundancy of the logic to guarantee safety metrics are satisfied, without the use of Software Test Libraries. This enables faster time-to-market and minimizing software integration work.


By the second half of 2023, two more product series will be added to the portfolio—the S7-A and X280-A. S7-A is an optimized 64-bit CPU tailored for safety islands requiring both low-latency interrupt support and the same memory space visibility as the main application CPUs. These are often used in ADAS, gateways, and domain controllers.

The combination of out-of-the-box features and design scalability enable designers to achieve a balance of power, performance, and area while achieving fast time-to-market for automotive MCUs, system controllers, battery-management systems (BMS), and safety islands for SoC markets. In addition to the automotive market, the E6-A series also is a good choice for broader deployment in MCU applications requiring functional-safety capabilities.


The X280-A is a vector-capable processor well-suited for edge sensing in ADAS, sensor-fusion applications, and any ML/AI-accelerated functionality in the vehicle. Building on the performance and power efficiency of the X280, it’s aimed at sensors, sensor fusion, and other vector or ML-intensive workloads in automotive applications.

SiFive’s growing portfolio of IP will range from small 32-bit real-time CPUs all the way up to high-performance 64-bit application processors. Later in 2023, a new high-end processor, configurable to up to 16 cores, will be added to the portfolio.

Read more articles in the TechXchangeRISC-V: The Instruction-Set Alternative

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