In the arena of business ethics, the phrase "do no harm" is central to the ideal of how businesses should conduct themselves. Variations on the theme such as "do no evil," adopted by Google's management, follow along the same thread. However, in a convoluted way, this same mantra has cast a less-than-flattering shadow on how IC designers view the task of the packaging engineer.
In this case, the term "do no harm" takes on a host of negative connotations. As far as the IC designer goes, whether referring to cost, signal disruption, power delivery, thermal dissipation, mechanical stress or soft error influence, the packaging engineer should not—under any circumstances—harm the chip's performance.
Considering that most companies do not sell bare die but rather packaged die, this is a very poor way to conduct engineering business. An automotive-engine manufacturing team cannot design an engine and then just tell the transmission engineering team not to screw it up. And, neither should chip design teams do so with packaging designers.
A more collaborative methodology needs to be implemented where chip design teams take packaging issues into consideration when developing the I/O and power delivery plan. These plans ultimately will depend on the package design and construction to meet performance expectations. To design them as separate entities without understanding and a failure to manage the interdependencies of chip and package can only result in missed expectations.
But it's not enough for design teams to agree to collaborate. The EDA industry must develop solutions that can enable this cross-domain collaboration to take place. Sketching I/O plans on the back of a napkin or capturing chip/package connectivity in a spreadsheet is not a viable methodology. Yet, these are the "tools" in place today to address and manage the complex interactions between chip and package.
With process nodes shrinking at a furious rate, the amount of functionality that chip designers can cram onto a chip is staggering. Combined with the increase in I/O speeds and lowering operating voltages, the stress on chip/package interaction can only ratchet up. Chip designers and EDA companies realized years ago that with the sheer number of factors to consider when dealing with millions of transistors on a chip, a new approach was needed. In fact, they determined that the most practical solution to solving these problems is to implement a synthesis approach and the electronics industry entered an era of synthesis-based design. We are at that same point now with the number of chip and package factors that must be considered to achieve a successful product.
Factors on the chip side that influence the chip-package I/O plan includes electrostatic discharge (ESD) protection, I/O sequencing, timing, power delivery, establishment of voltage regions, die size, core size, electrical constraints, redistribution layer (RDL) and many more. On the package side, there are factors such as escape routing, process rules, voltage domain isolation, assembly rules, signal and power integrity and package/PCB routing, to name a few.
All these factors will have a direct impact on performance, cost containment, time to market and profitability. A synthesis approach that can take all or some of these factors into consideration early in the process will enable the design teams to take a more holistic approach to chip and package interaction. They will be empowered to make more informed decisions on the tradeoffs that will inevitably take place.
"Do no harm" can no longer be the mantra imposed on package design engineers. Instead, chip and package teams need to work as a unit. Companies sell packaged chips and they need to design them that way.
