National Semiconductor's LVDS buffer features low jitter, ESD protection

National Semiconductor Corporation has introduced the DS90LV804, a four-channel LVDS buffer that operates from zero to 800 Mb/s and features 30 psec total typical jitter and 15 kV ESD protection for isolation of FPGAs, ASICs and other onboard components. The device is designed to deliver clean LVDS signals across cables and backplanes in automotive and other applications.

The DS90LV804 drives up to four LVDS clock and/or data channels. Its differential input range interfaces to LVDS, low-voltage positive emitter-coupled logic (LVPECL) or current-mode logic (CML) input levels, and its output levels are fully LVDS compliant. With internal input and output or source termination resistors to guarantee low return loss during data transmission, as well as to reduce parts count, the device can serve as a signal integrity driver for clock and data signals. Its quad configuration has matched output drivers for 50 psec typical minimal channel-to-channel skew. On-board terminations reduce jitter by terminating the signal path at the transmit output and at the receiver input.

The DS90LV804 is available in a 32-pin LLP package that measures 5 x 5 x 0.80 mm.