Electronicdesign 25041 Armheliosae Promo

More Arm Split-Lock Cores for Automotive Apps

Dec. 20, 2018
Arm extends its reach into the automotive space with the new Cortex-A65AE that includes split-lock support.

Arm has had lockstep cores since its Cortex-R family, which targets safety applications such as automotive where redundancy is important. Even FPGAs have incorporated hard-core Cortex-R processors. Earlier, the company announced that its Cortex-A76E for automotive applications included a feature called split-lock that allows developers to select how cores operate together or are separated. This approach makes it possible to consolidate multiple chips into a single SoC while providing the same level of safety assurance (Fig. 1).

1. Integrating multiple processors into a single SoC that still meets safety standards can be accomplished with Arm’s split-lock support.

Arm’s latest automotive-enhanced (AE) processing core is the Cortex-A65AE. It features the split-lock support provided by the Cortex-A76AE, which allows a designer to configure a mix of isolated clusters, including dual cores in lockstep mode (Fig. 2). These SoCs can meet ASIL-D and ISO 26262 requirements needed for advanced driver-assistance systems (ADAS) and self-driving cars.

2. Split-lock allows a system to be configured at runtime. Clusters can be isolated by hardware and locked clusters provide redundancy as prescribed by designers.

The Cortex-A65AE targets 7-nm silicon and delivers multithreaded support. It’s designed to manage high-speed input from a large number of sensors such as LiDAR, radar, and visible infrared and thermal cameras. The cores can be integrated with Arm’s machine-learning (ML) accelerators.

Like the Cortex-A76AE, the Cortex-A65AE memory protection’s support includes single error correction, double error detection (SECDED) ECC and parity protection in the L1 cache, and SECDED ECC protection with the ability to correct errors in-line for the L2 and L3 caches.

Likewise, the Cortex-A65AE supports the reliability, availability, and serviceability (RAS) specification of the ARM 8.2 extensions. This includes standard error reporting across the core and the DynamIQ Shared Unit (DSU). It supports error injection for testing fault management as well as data poisoning to check deferring error aborts till point of execution. The entire AE platform is supported by the Arm Safety Ready program.

Sponsored Recommendations


To join the conversation, and become an exclusive member of Electronic Design, create an account today!