Large macros and memories used in
system-on-a-chip (SoC) designs can
save time, but they can also be a bear when it comes to verifying them from
a power-integrity standpoint. Their internal
physical and logical complexity, along with
their sheer size, can be too much to handle for transistor-level analysis tools. Such
tools can perform accurate voltage-drop
analysis on each transistor's current waveform, but they lack the capacity for the job.
Sequence Design's macro modeling
technology creates highly accurate representations of macros for chip-level power-integrity analysis while sidestepping the
capacity blues. The Sequence Macro Modeling using Advanced Region Technique
(SMMART) will enhance Sequence's Cool
Products power-integrity tools by overcoming the lack of adequate characterization
data in Liberty (.lib) energy models.
SMMART modeling enables CoolTime,
Sequence's power-grid integrity product, to
handle spatial current modeling of macros
and memories with weighted distributions
for different memory sections (called
regions in CoolTime, e.g., decoders, sense
amps, or bit arrays; regions can be user-defined as well).
Also, the tool can perform temporal
modeling for various modes of operation,
modeling the current over time from the
Synopsys .lib models. Doing so requires
characterized current waveforms from a
fast-Spice simulator, such as HSIM. Modeling can be performed using a single
waveform per memory or multiple waveforms per region ().
CoolTime now also offers a 40% reduction in memory footprint and runtime for
dynamic voltage drop analysis and a tenfold improvement in disk usage for
dynamic voltage drop optimization. Hold
time optimization algorithms now insert
up to 20% fewer buffers to limit engineering change order changes, accelerate
design closure, and reduce power as well.
Contact Sequence directly for pricing
and delivery information.
Sequence Design
www.sequencedesign.com
