Memory Directions: Speed, Speed, And Density

In general, the faster data can be retrieved, the faster the host processor can execute its algorithms. Internal parallelism on the processor side requires ever-faster data-transfer rates from external memory to keep parallel execution units active. In the DRAM world, this has translated into the move from single-data-rate synchronous DRAMs (SDRAMs) to double-data-rate (DDR) SDRAMs down one path and to the use of Rambus' DRAM (RDRAM) down a second path. A third fork for specialized low-latency applications, such as that found in network subsystems, has produced a reduced-latency DRAM (RLDRAM) that's optimized for real-time packet-handling subsystems.

Already, the first-generation DDR interface, which peaked at 333 to 400 MHz and memory densities of 512 Mbits (although at least one company is sampling 1-Gbit devices), is giving way to the second-generation version, DDR II, which offers data-transfer rates starting at 400 MHz. Over the next two years, DDR II data rates will peak at 667 to 800 MHz, and available memory densities will increase from today's 256- and 512-Mbit devices to 1 Gbit/chip. A third-generation DDR interface will offer still higher data rates. However, samples probably won't be available until late 2004 or early 2005.

Yet many designers still look for even faster data-transfer rates. Answering that demand, several companies developed new memory-interface architectures that promise to boost transfer rates to more than 6 Gbytes/s. Later this year, Toshiba and Infineon Technology both expect to sample DRAMs based on Rambus' extreme-data-rate (XDR) interface.

The XDR approach requires a full revamping of the DRAM interface and a new point-to-point memory subsystem that may take a while to be accepted by mainstream systems. Another approach, slated for introduction this quarter by Silicon Pipe Inc., employs a controller chip that sits between the host processor and the memory array and multiplexer chips that connect the controller to the memory array. This scheme, which can use standard DDR memory DIMMs, achieves throughputs of up to 12.8 Gbytes/s.

High-speed static RAMs haven't changed much over the last year due in part to the slowdown in the telecommunications and networking markets. The quad-data-rate SRAM has established itself as the high-speed solution, and it comes in 18- and 36-Mbit versions. Also well established are the no-bus-latency SRAMs, which dominate networking applications.

Regaining some popularity in mobile systems is the pseudostatic RAM. Outwardly, it functions like an SRAM. But internally, it uses a DRAM core and circuitry to make the DRAM array operate like a static RAM. This allows for a much higher bit capacity for the same chip area. The DRAM core also consumes less power than the SRAM core, especially during idle periods, because refresh currents are lower than leakage currents in most high-performance SRAMs.

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• COMMERCIAL VOLUMES OF 1-GBIT DDR SDRAMs will be available from several memory suppliers. Yet initial volumes will be absorbed mainly by server manufacturers because costs will be too high for the commodity memory market.
• THE FIRST SAMPLES OF 4-MBIT magnetoresistive memory will be available from Motorola. These memories combine the best aspects of flash memory and SRAM, offering fast and symmetrical read and write operation, unlimited writes, nonvolatile storage, and relatively good densities.
• PRODUCTION QUANTITIES of DDR II SDRAMs will be available in 400- and 466-MHz speed grades before mid-year, and samples of 533-MHz versions are expected sometime late in the coming year.
• SAMPLES OF 512-MBIT RAMBUS RDRAMs will be available this quarter. In addition, 256-Mbit devices will be available in speed grades of 600 to 800 MHz.
• EXPECT SAMPLES OF THE FIRST EXTREME-DATA-RATE DRAMs to be released by Toshiba Corp. These memories incorporate a differential interface developed by Rambus Inc. that will transfer data at up to 6 Gbytes/s. The first device will pack 512 Mbits. A scaled-down 256-Mbit version is already on the drawing boards for later release.
• THE SPECIFICATION FOR 2G FAST-CYCLE DRAMs with capacities of 576 Mbits will be finalized this year. Engineering samples of prototype devices will be released by mid-2005. Meanwhile, 512-Mbit 1G devices will be commercially available in the first quarter of this year.
• PROTOTYPES OF THE FIRST nanocrystal-based flash-memory chip will be demonstrated by Motorola. This technology, an extension of standard CMOS processes, uses a layer of 50-angstrom silicon dots deposited on a 50-angstrom grid that lies on top of a thin oxide layer.
• FLASH-MEMORY DEVICES with 2 Gbits of single-bit/cell storage capacities will be commercially available this year, with still higher density devices on tap for 2005. This year will also see availability of 4-Gbit dual-bit/cell flash devices.
• LOOK FOR A HIGH-SPEED MEMORY interface from Silicon Pipe as an intriguing alternative to the XDR interface. The novel interface design employs a controller that converts the parallel bus of a host system to serial interfaces. In turn, the interfaces connect to small multiplexer circuits that talk to standard DRAM modules.
• SAMPLES OF 36-MBIT QUAD-DATA-RATE SRAMs should be readily available from several manufacturers, with production quantities ready by mid-year.