Imperas 5f6d9c4e0e41c

NSITEXE Taps Imperas for Development and Verification of Next-Gen RISC-V Automotive Processor IP

Sept. 25, 2020
RISC-V Vector Instruction Extension for Automotive applications to be verified with Imperas proprietary code-morphing simulation technology, verification tools, and validation suite.

Imperas Software, a provider of virtual platforms and high-performance software simulation, confirmed the selection by NSITEXE, a group company of DENSO, a developer of advanced semiconductor IPs, for the development and verification of the next-generation Automotive processor IP based on RISC-V with vector instruction extension. RISC-V is an open ISA (Instruction Set Architecture), which permits many configurations and options for processor implementation and microarchitectural features.

The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles.

Virtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors, as well as user defined custom instructions, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow.

As the project develops to the next phase, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early compatibility with the growing ecosystem supporting RISC-V vectors. 

The latest RISC-V vector instruction extension specification is fully implemented within the Imperas RISC-V reference model. riscvOVPsim is a free single-core model and simulator which is available on GitHub for both commercial and non-commercial use at https://github.com/riscv/riscv-ovpsim. riscvOVPsim is also the reference model as used by the RISC-V International Compliance working group developing the official reference compliance suite which will be used by all implementers, adopters and ecosystem partners.

The latest official compliance suite is available at: https://github.com/riscv/riscv-compliance. 

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