Electronic Design
DDR Memory Systems Compensate for Variations

DDR Memory Systems Compensate for Variations

Uniquify’s DesignCon booth (#317) will be showcase the company’s DDR4 memory IP (2800 Mb/s) and DDR3 memory system in a wirebond package. Dynamic self-calibrating logic (DSCL) circuitry for both helps measure precise timing windows and automatically adjusts them for each system to compensate for static and dynamic variation. Combined with dynamic adaptive bit calibration (DABC) technology, the compact, low-power DDR systems offer high reliability and improved device yield. Each DDR subsystem IP includes a flexible and configurable DDR memory controller, a DFI-compliant PHY (incorporating both DSCL and DABC technology), and high-performance DDR I/Os.


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