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Integrated Host Processor Employs RapidIO Technology

Leveraging a system-on-chip design platform, the MPC8540 integrated host processor is the companyÕs first such device to include RapidIO interconnect technology. RapidIO, an open standard governed by an independent industry body, offers significantly greater bandwidth, scalability and reliability than current interconnects, yet is compatible with existing PCI and CPU architectures. The new processor, based on the companyÕs e500 core, integrates dual gigabit Ethernet controllers, a 10/100 Ethernet controller, 64-bit PCI-X controller operating at up to 133 MHz, DDR memory controller, four-channel DMA engine, multi-channel interrupt controller, and a DUART serial interface. Other features of the host processor include 256 KB of on-chip L2 cache, a coherency module that connects the core and memory controller to processor peripherals, and a unique non-blocking crossbar switch fabric called OCeaN (On-Chip Network) that enables full-duplex port connections at 128 Gb/s concurrent throughput and independent per port transaction queuing and flow control. The processor is expected to become available in versions that span operating speeds of from 600 MHz to 1 GHz with power consumption of 6.5W at 800 MHz. Samples are expected to be available in the second half of this year. For further details, call Sarah Spreitzer at MOTOROLA INC., Tempe, AZ. (512) 933-7753.


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TAGS: Digital ICs
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