Electronic Design
All images courtesy of Analog Devices Inc

All images courtesy of Analog Devices Inc.

Multicore DSP SoC Incorporates Cortex-A5 for Connected Signal Processing

Analog Devices’ ADSP-SC589 (Fig. 1) pairs two SHARC+ DSPs with an ARM Cortex-A5 to handle connected and demanding signal processing chores. This System-on-Chip (SoC) draws less than 2 W while delivering an overall performance of 24 GFLOPS. Each DSP core delivers 5.4 GFLOPS and 1.8 GMAC/s. A low-power FFT/iFFT accelerator adds up to 18 GFLOPS; it can handle up to 2048-pt complex FFT/IFFT using a dedicated, high-speed DMA controller with pipeline mode. The DSP engines are also augmented with FIR and IIR filters, SINC filters for motor control, and Harmonic Analysis Engines (HAE).

The SHARC+ cores share a crossbar switch with a shared L2 ECC cache and dual DDR interfaces. Each core has its own L1 parity-enabled cache. The system has 1.5 Mbytes of on-chip memory. The switch provides access to an array of peripheral I/O, including USB 2.0 and PCI Express Gen 2 interfaces. Two high-speed link ports allow multiple SoCs or ADI DSPs to be added to the mix. Communication links include serial ports, a pair of CAN 2.0 ports, and two 10/100 Ethernet MACs with AVB support. There also is an eight-channel, 12-bit ADC.

1. Analog Devices ADSP-SC589 pairs two SHARC+ DSPs with an ARM Cortex-A5, as well as hardware accelerators and glueless audio interfaces. (Click for enlarged view.)

Typically the ARM Cortex-A5 will handle communication chores. Applications likely will take advantage of the security cryptographic engines. The security features includes on-chip OTP for secure boot and network security support. The hardware can handle AES-128 and AES-256.

Developers can get started with the ADSP-SC58x EZ-KIT (Fig. 2). The board is supported by Analog Device’s CrossCore Embedded Studio as well as third-party tools. CrossCore handles both the SHARC+ DSP cores and the ARM Cortex-A5. The kit comes with a one-year license and an ICE-1000 JTAG emulator. There is a functional and cycle accurate SHARC+ simulator to address timing critical applications. The system has a unified breakpoints, single step, and trace facility.

2. The ADSP-SC58x EZ-KIT works with Analog Devices’ CrossCore Embedded Studio.

Linux is available for the ARM Cortex-A5. The Micrium µC/OS-III can run on ARM and SHARC+ cores. It supports the Multicore Association’s Multicore Communications API (MCAPI) for Inter-Core Communications (ICC). Linux also supports MCAPI, allowing a Micrium µC/OS-III/Linux computing combo.

Analog Devices also provides the System Services and Device Drivers (SSDD) package. This code can run on either type of core. There is a graphical interface for configuration program as well. Source code is provided.

The family consists of eight new devices, including the ADSP-SC58x with Dual SHARC+ and a Cortex-A5, as well as the ADSP-2158x with only the two SHARC+ cores. The chips are available in a 19-mm by 19-mm, 529-BGA. Pricing starts at $17. 

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