The goal of electronic design automation (EDA) has always been to improve design productivity. But with the next generation of tools on its way, EDA will have to change the methods it uses to achieve that goal.
This industry has come a long way from its early days of schematic capture and rudimentary logic simulations. Language-based design and verification have driven second-generation EDA productivity. They automated the implementation and optimization of design elements.
With the proliferation of multimillion-gate system-on-a-chip (SoC) designs, optimization is no longer the main barrier to productivity. In its new phase, EDA is focused on solutions for complete systems on a piece of silicon, such as analog and digital. The operation of these systems is equally dependent upon several components, including the silicon's embedded-software content, hardware processors, memory blocks, and peripherals.
This period in EDA development stands out for its pursuit of system design productivity. It will accomplish this through design reuse, customized design environments, and web-based communications.
The availability of intellectual-property (IP) libraries is critical to SoC design. This issue will be a mainstay of the next generation of EDA. Much more than a collection of design blocks, the IP must convey how a design block was created.
Future designers will need help making modifications. They'll be looking for methods of inserting test or performing optimizations. Verification suites and test vectors need to be saved and reused. Information about the original design methodology and flow are crucial. These factors can help determine the best way to integrate and verify a block in a system. By applying this data, reusable parts can be converted into true IP. EDA environments must manage and use this information to improve SoC design productivity.
An SoC design involves a lot more than a group of design blocks, however. It includes IP associated with the architecture, bus interconnections, embedded software, and verification methods.
EDA environments are currently being customized to meet the requirements of individual SoC applications. These environments take the form of design-reuse reference platforms and application-specific flows.
The application-specific platforms attempt to reuse all of the work that goes into a system. From that starting point, they rapidly create new designs. For example, the optimal EDA environment for a cable-modem SoC design should contain IP consisting of design data, flows, software, and verification methodologies. It also must be capable of re-applying that IP to generate new cable-modem technology. A similar environment for a mobile-phone chip might use many of the same tools. But it would consist of a totally different set of customized IP.
Essential to using this IP is the web. Many EDA platforms rely on it for communications. The web helps designers obtain correct data that comes complete with flows, verification suites, and documentation. Then it automates the reuse of that information in a system. Through web-integrated EDA environments, designers can share data and best practices globally. Communication between designers and vendors is improved as well. As a result, the functionality and support of tools for specific applications is optimized.
The applications are as limitless as the Internet's potential. The benefits to be reaped from next-generation EDA also are a current reality.