Electronic Design

Turbocoder IP Cores Keep Bit-Error Rates Low

Throughput of 1 Mbit/s with performance of 1.5 GOPS is featured in a family of turbocoder IP cores from Adelante Technologies. Turbocoding is used for forward error correction in a variety of wireless data communication systems, including 3G/UTMS and CDMA/CDMA 2000 mobile phones, digital video broadcasting systems, satellites, xDSL systems, wireless LANs and PDAs, and high-speed fiber-optic systems. The family includes a turbo encoder, a turbo decoder, and a full-duplex turbocoder that combines both encoding and decoding functions.

"Turbocoding is a mandatory part of several evolving communication standards," says Herman Beke, Adelante's chief operating officer. "The only realistic way to create an SoC with low power and enough processing throughput to handle turbocoding is with a highly optimized, application-specific core."

Turbocoders perform error correction using two convolutionally encoded streams. The first data stream is input in the order in which it was transmitted. The second is input in interleaved order. For each data stream, the probabilities are calculated that each originally transmitted bit is a 1 or 0 using a maximum aposteriori (MAP) decoder. Feeding these probability results from one MAP to a second MAP increases the accuracy of the error correction.

The cores use the Log MAX algorithm for encoding and decoding, which requires about 1.5 GOPS. This level of performance is difficult to implement on standard hardware architectures. Adelante has created a highly parallelized architecture that executes both of the cores' MAP decoders in a single clock cycle. The single-cycle MAP execution gives the cores throughput of 1 Mbit/s (based on a 5114-bit block) with a clock rate of just 8.2 MHz. Bit-error rates are 10 −6 at a signal-to-noise ratio of 1.5 dB.

Typically, turbocoders require about 8 kbytes of SRAM for encoding and 37 kbytes of SRAM for decoding to buffer the alpha metrics. Use of memory windowing technology in these cores has reduced total memory requirements to just 1 kbyte for encoding and 6.3 kbytes for decoding.

All three cores are available in synthesizable VHDL or Verilog and are verified using Artisan Components' TSMC 0.18-µm standard cell library. They come with cycle- and bit-accurate ANSI C++ or SystemC models for high-speed SoC verification. They're also available in high-level C++, in combination with Adelante's A/RT Designer IP generation tools, enabling users to generate customized versions. Prices start at $70,000.

Adelante Technologies, Abdijstraat 34, 3001 Leuven, Belgium; +32 16 39 14 11; www.adelantetech.com.

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