Electronic Design

Accellera Works On Interoperable Verification Standards

Accellera, the electronics industry organization focused on EDA standards, has formed a verification standards committee to define standard technology and/or methods to realize a modular, scalable, and reusable generic verification environment. The goal of the Verification Intellectual Property (VIP) Technical Subcommittee is to reduce verification costs and improve design quality.

Verification components and environments are currently created in different forms, making interoperability among verification tools or geographically dispersed design teams time-consuming and error-prone. Accellera said that its VIP standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting IP for each new project or electronic design automation tool, as well as make it easier to reuse verification components.

“Accellera is addressing the electronic design industry’s need for a common standard for Verification IP interoperability and reuse,” said Shrenik Mehta, chair of Accellera. “Our newest VIP Technical Subcommittee’s goal is to improve design productivity by making it easier to verify the design components with a standardized representation that can be used with various verification tools.”


TAGS: Intel
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