Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. Using the "Open Verification Methodology" (OVM), designers and verification IP providers will be able to create models and testbenches in one format that will work with any OVM-compliant tool environment. The OVM will be open-source and available under the standard Apache 2.0 license. "The OVM solves one of the biggest issues facing SystemVerilog adoption today," Robert Hum, vice president and general manager of Mentor's verification and test business unit, said in a statement. "Customers seek confidence that their investments in verification will be reusable in the future. Having a methodology that works on a number of widely installed simulators and verification tools provides the confidence to move to SystemVerilog." The OVM supports a mix of RTL and transaction-level abstractions for SystemVerilog and other high-level languages that support system-level design and verification. Select release is slated in the third quarter of this year, with a larger production release that includes the methodology and supporting library in the fourth quarter.