Intel And Glasgow University Team Up On Nanoscale Memory Design

Glasgow, Scotland: A European Commission taskforce has been set up to investigate how to design the next generation of tera-scale computer memory systems, as microchips are expected to incorporate billions of transistors within the next decade.

As transistors get smaller, tiny variations within their structures affect their performance and thus the reliability of the whole microchip. This problem presents a huge barrier to the continued scaling of microchips and the development of ever-more powerful computers.

To overcome this obstacle, the Tera-scale Reliable Adaptive Memory Systems (TRAMS) consortium will develop ways of designing future microchip memories that account for the variability and unreliability of nano-scale transistors. The group includes Intel Corporation Iberia, Interuniversitair Micro-Elektronica Centrium vzw, the University of Glasgow, and the Universitat Politecnica de Catalunya.

Professor Asen Asenov of the Department of Electronic and Electrical Engineering is leading the University of Glasgow’s involvement at the heart of the project. He is an authority on the variability of CMOS technology. Central to the project is simulation software developed by Asenov in an earlier £5.3 million Engineering and Physical Sciences Research Council eScience pilot project called NanoCMOS. The Nano-CMOS simulations use grid computing, which utilizes the processor power of thousands of linked computers, to simulate how hundreds of thousands of transistors, each with their own individual characteristics, will function within a circuit.

Asenov and the University of Glasgow are setting up a company called Gold Standard Simulations to exploit this technology, which will be critical to the work of the TRAMS project. All device design and simulation work will be conducted at the University of Glasgow.

In investigating design possibilities for future microchips, the team will focus on the future generation of CMOS microchip technologies, which comprise transistors less than 16 nm. (A human hair is around 100,000 nm wide.) The University of Glasgow will design and simulate the transistors exclusively. The project is expected to last three years.

TAGS: Intel
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