FPGA supplier Lattice Semiconductor and analog chipmaker Silicon Laboratories will cooperate to market ITU G.707 and GR-253-CORE compliant solutions for telecom applications. Lattice will offer its LatticeSC/M FPGAs with built-in SONET PCS blocks — the SONET flexiPCS block — in conjunction with Silicon Labs' Si5023 multi-rate clock and data recovery (CDR) device, new Any-Rate Si570 programmable crystal oscillator (XO) and Si5326 Any-Rate precision clock. The Silicon Labs multi-rate CDR, XOs and clock products — which ensure compliance with SONET/SDH jitter specifications — can be used in conjunction with the LatticeSC FPGA for a complete SONET solution. Silicon Labs' Si5023 multi-rate CDR minimizes data jitter associated with LatticeSC's SERDES outputs, while its crystal oscillator and clock devices provide reprogrammable reference clock frequencies to the FPGA. "By joining Silicon Labs' innovative timing solutions with a Lattice FPGA, we are ensuring a seamless solution for a challenging design problem for our customers," David Bresemann, vice president of Silicon Laboratories, said in a statement. "We are very pleased to announce our cooperation with Silicon Laboratories to provide our mutual customers with programmable TDM solutions that meet the strict performance and jitter criteria for SONET/SDH compliance," Stan Kopec, Lattice corporate vice president of marketing, said in a statement.