The package includes the Blast Fusion physical design system. This feature performs full chip design. It also sports a multimillion-gate capacity. Blast Fusion performs synthesis, logic optimization, clock, power and timing estimation, extraction and place and route, and signal integrity and congestion management. Designed to take full chips and large designs from RTL through GDSII, users can base partitioning on design or project management requirements, rather than on tool capacity limitations.
Several licensing options are available. Each comes with a three-year, time-based model. Blast Chip licenses start at $415,000 a year. Blast Fusion licenses start at $385,000 a year. Optional licenses for Blast Noise, which prevents and corrects signal integrity problems, start at $150,000 a year. All versions ship on Solaris and HP-UX workstations.
Magma Design Automation, 2 Results Way, Cupertino, CA 95014; (408) 864-2000; fax (408) 864-2001; www.magma-da.com.Software Tool Generates Over 4000 Process-Specific I/O Devices The I/O Compiler software tool lets ASIC designers create a complete portfolio of process-specific I/O devices. Users can choose from a wide variety of features for each input, output, bidirectional, three-state, power, and ground-pad type through its user-friendly interface. These features include pad pitches, operational voltages, voltage tolerances, and performance and testability options. Its manufacturer says these features provide design flexibility and quality, producing a physical I/O layout supported by leading EDA tools.
This tool has been silicon proven. It can generate over 4000 distinct I/O devices based on the combination of features selected. All I/Os conform to ESD and electrical guidelines, ensuring high yield and reliability. By supporting the generation of front-end design models and automatically implementing the physical back-end views, the I/O Compiler shortens the product development cycle. Also, it supports the 0.18-µm CMOS process while addressing analog and digital noise isolation issues.
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Nurlogic Design Inc., 9710 Scranton Rd., Ste. 380, San Diego, CA 92121; (877) NURLOGIC, (619) 455-7570; fax (619) 457-5578; www.nurlogic.com.Infrastructure Permits Remote Collaboration And Management CreOweb, an e-design/e-management infrastructure for web-based, business-to-business engineering environments, lets remote designers collaborate in all engineering and management phases. Its groupware solutions provide the ability to access and display physical databases through the Internet. It features a strong-server/thin-client architecture, accelerates time-to-market, and eliminates costly handoffs and delays. Several important applications are included as well.
SiliconCruiser gives users remote access to the back-end placement and routing information database anytime, anywhere through any existing browsers. GdsCruiser is an interactive layout viewer, while PackageCruiser is an IC packaging design viewer. DwgCruiser provides the fastest, most accurate way to view and distribute design drawings without the constraints of time, location, or availability of the drawing tools. CreOx enables web-based, real-time desktop application sharing. And, CreOflow conducts project/flow management.
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CreOsys Inc., 39560 Stevenson Pl., Ste. 221, Fremont, CA 94539; (510) 796-1111; fax (510) 796-2445; www.creosys.com.Design Environment Update Doubles Verilog Code Coverage Performance The Verification Navigator integrated design environment has been upgraded to version 6.1. Its new test-suite optimization engine increases capacity by over 100 times, enabling reduced simulation time for extremely large regression test suites.
A broad array of optimizations initially targeted at the most commonly used coverage metrics have resulted in a dramatic increase in Verilog code-coverage performance. Compared with earlier versions, version 6.1 has achieved an average of 2.3-fold lower simulation overhead over a large number of designs.
Its VN-Optimize test-suite optimization tool features a completely re-engineered optimization engine built to support test suites containing over 100,000 individual test sets. This tool also lets designers reduce test simulation time by identifying redundant tests and by sorting tests in order of their effectiveness.
Verification Navigator 6.1's base price starts at $20,000. Existing customers under maintenance will receive the new release for free.
TransEDA, 985 University Ave., Los Gatos, CA 95032; (408) 907-2000; fax (408) 907-2085; www.transeda.com.Standalone Verilog Simulator Meets IEEE 1364-95 Standard Active-HDL/VLOG, a standalone Verilog-compliant simulator, offers complete OVI compliance and PLI support as well as seamless integration between design entry and simulation debugging software. Its Verilog simulation kernel, supported from within the Active-HDL design environment, includes Verilog design entry, testbench generation, and high-performance direct compile Verilog simulation. Built-in Verilog primitives provide quick compile times and fast simulation as well.
This simulator completely supports the IEEE 1364-95 standard for compatibility with all existing Verilog designs. Full programmable logic interface, standard delay format, and value change dump are supported as well. With this IEEE compliance, users can simulate any design, design section, or IP core developed in any popular HDL design tool. Active-HDL/VLOG also includes a project manager, an HDL editor, a state machine editor, a block diagram editor/schematic editor, and a waveform viewer and editor.
Pricing starts at $5200. Free evaluation copies are available.
Aldec Inc., 2230 Corporate Circle, Henderson, NV 89014; (800) 487-8743; fax (702) 990-4414; www.aldec.com.