EDA Tool Update

July 7, 2003

The OpenAccess application programming interface and database has seen another successful port. Cadence's Virtuoso Chip Editor chip finisher, which takes ICs through the final stage of design implementation, exploits the OpenAccess interface to eliminate a data logjam between Cadence's SoC Encounter design suite and Virtuoso. For details, see www.cadence.com.

Verisity and 0-In Design Automation are collaborating to report integrated verification coverage metrics to their customers. The coverage information available in Verisity's Specman Elite testbench automation tool will include both native functional coverage metrics and the structural coverage metrics from 0-In's CheckerWare assertion checkers and monitors. Visit www.0-in.com and www.verisity.com.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.