Sequential Power Optimization Tool Pinpoints Clock-Gating Opportunities At RTL

By applying sequential analysis techniques at the register-transfer level (RTL), Calypto Design Systems' PowerPro CG identifies microarchitectural changes that result in a lower-power circuit. According to Calypto, initial customer designs have seen po

David Maliniak

March 29, 2007

By analyzing the sequential behavior of synthesizable RTL designs across multiple clock cycles, PowerPro CG identifies chip regions that can be clock gated to reduce dynamic power. It then automatically generates the clock-gating enable logic in much less time than error-prone manual methods.

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and switching activity file formats, so the power savings achieved by PowerPro CG are added onto optimizations performed by synthesis and placement tools downstream.

Available now, PowerPro CG runs on PC platforms running Linux. Contact Calypto directly for pricing information.

Calypto Design Systems
www.calypto.com

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.