By applying sequential analysis techniques at the register-transfer level (RTL), Calypto Design Systems' PowerPro CG identifies microarchitectural changes that result in a lower-power circuit. According to
Calypto, initial customer designs have seen power reductions of up to
60% without any impact on functionality, area, or performance.
By analyzing the sequential behavior of synthesizable RTL designs
across multiple clock cycles, PowerPro CG identifies chip regions
that can be clock gated to reduce dynamic power. It then automatically generates the clock-gating enable logic in much less time than
error-prone manual methods.
Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits
into existing design flows with industry-standard library, timing, and
switching activity file formats, so the power savings achieved by
PowerPro CG are added onto optimizations performed by synthesis
and placement tools downstream.
Available now, PowerPro CG runs on PC platforms running Linux.
Contact Calypto directly for pricing information.
Calypto Design Systems
www.calypto.com