EDA Update: Hardware/Software Coverification Tool

Oct. 27, 2003

Developed for FPGAs using soft-core CPUs, Aldec's CoVer hardware/software coverification tool targets embedded-system design. It combines Aldec's Active-HDL design-entry package with new CoVer technology that enables software and hardware teams to work concurrently on the same design configuration. The tool, which supports the Xilinx MicroBlaze and Altera Nios processors, costs $15,900. For details, visit www.aldec.com.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.