Dealing With Shades Of Gray

Jan. 11, 2007
The phrase "knowledge is power" applies particularly when the semiconductor industry grapples with comprehending the impact of variability and improving parametric yields. Statistical static timing analysis, viewed as the panacea for parametric yield iss

The phrase "knowledge is power" applies particularly when the semiconductor industry grapples with comprehending the impact of variability and improving parametric yields. Statistical static timing analysis, viewed as the panacea for parametric yield issues, is still evolving. That's because it lacks availability of adequate information and a robust model for the process, devices, and libraries.

In addition, designers don't know what action to take based on a distribution. Designers, who have historically dealt with black and white models, now must deal with statistical tools full of shades of gray. To resolve the parametric yield challenge and rapidly migrate designs to 65 nm and below, a complete statistical manufacturing and design analysis methodology that extracts and leverages intelligence from process information must be adopted.

To optimize parametric yields for sub-65-nm processes and design, a global yield-optimization methodology is needed. In such a methodology, manufacturers would adopt statistical electrical metrology techniques that can provide massive amounts of electrical data. Data of this nature would help them characterize the within-die performance and yield impact of physical effects such as random fluctuations exemplified by line-edge roughness (LER) and dopant fluctuations.

Such electrical data would also enable direct measurement of electrical parameters that designers care about, such as VT, ION, IOFF, resistance, and capacitance. It would additionally let designers build statistical models that capture electrical parameter variability while obfuscating the fab's physical process intellectual property.

Moreover, such a global yield-optimization methodology would facilitate a movement toward statistical design-analysis techniques that use secure statistical models based on electrical parameters at cell and device/interconnect/circuit levels. It can aid in analysis of the parametric yield impact of process variability on design. And, it can make a distribution "actionable."

We love to see rosy forecasts for the future. In fact, astrologers and tantrics who illustrate a future full of green pastures roll in more green (i.e., money) than those who show a more realistic picture potentially including shades of gray. In 2007, the semiconductor and EDA industries will see many green and some red patches, and without a doubt, will deal with shades of gray!

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