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This laptop-size test system, called Validator 500, is designed to dramatically reduce the time needed to validate and debug Design-for-Testability (DFT) test programs and test structures for new system-on-a-chip (SoC), ASIC and other complex integrated circuits. Among the types of DFT-related testing performed on the test structures (circuitry) of these ICs are internal and boundry scan, built-in-self-test (BIST), and quiescent current (IDDQ). Using proprietary, DFT-Intelligent software, the Validator 500 system imports both test patterns and structural information about an IC’s DFT. The system simplifies test preparation by directly importing the automatic test pattern generation (ATPG) scan test data in IEEE 1450 (STIL) format. The Validator 500 has the capability to address devices with greater than 100 internal scan chains and multiple clock domains at rates up to 50 MHz with up to 32-million pattern vectors. Promising quick detection and identification of odd DFT behaviors, users can navigate across both structural and tabular views of the same test data. Available in December, the system is priced at $60,000. TESEDA CORP., Portland, OR. (503) 223-3315.