EDA Update: ASIC Prototyping Support

Dec. 4, 2003

ASIC prototyping support has been built into Hier Design's PlanAhead hierarchical floorplanning and analysis software. The tool, which automates the design and integration of IP blocks within FPGAs, has been shown to help designers more quickly create FPGA prototypes for verifying ASIC designs. PlanAhead uses a block-based methodology that allows designers to "carve out" logic blocks from their ASIC designs and place them on an FPGA for prototyping. They can then optimize blocks for performance and test them with related software. As a result, ASIC prototypes run at a much higher speed than is possible with traditional emulation. A time-based license for PlanAhead costs $25,000/year; it runs on Solaris, Windows and Linux platforms. For details, visit www.hierdesign.com.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.