It's now the rule rather than the exception: Logic designers must accept
responsibility for verification. But time is
short, so it behooves EDA vendors to
enhance verification productivity. In the
latest improvements to its Logic Design
Team (LDT) portfolio of verification tools,
Cadence addresses three key bottlenecks
that hamper productivity ().
Cadence has beefed up the formal
engine in its Incisive Formal Verifier, providing a 5 × to 50 × gain in both speed
and capacity. The LDT flow is now better
positioned to enable designers to adopt
standard assertion languages. A second
improvement is in the LDT portfolio's ties
to hardware simulation acceleration. The
functional blocks that designers are
responsible for are becoming large
enough for acceleration to be helpful.
Designers find themselves using constrained-random, coverage-driven testbenches on their million-plus-gate blocks.
Cadence's answer is a "hot-swap"
capability between its Xtreme hardware
accelerator and the Incisive Simulator. A
seamless interface between the simulator and the hardware accelerator lets
users switch between them in seconds.
Now, 100 million clock cycles take 11.5
days on the simulator but just 2.4 minutes on the Xtreme accelerator.
Lastly, Cadence has addressed the
amount of time it takes to set up an
assertion-based verification environment.
Packages of verification IP (VIP) are available for the AMBA AHB and AXI protocols
as well as the Open Core Protocol.
The LDT verification portfolio is available now. Contact Cadence for pricing.
Cadence Design Systems
www.cadence.com
