Program Enables SoC Verification Collaboration Among Vendors

Oct. 15, 2001

A new partner program will integrate best-in-class system-on-a-chip (SoC) verification tools from 10 vendors. Aimed at reducing the time-to-market crunch caused by the verification cycle, Axis Systems' FastLink program will give customers a fast and complete environment for the entire verification flow by linking partners' solutions with Axis' ReConfigurable Computing (RCC) engine.

"As much as 80% of the design cycle is now absorbed by verification," said Steve Wang, vice president of marketing at Axis. "It's a problem crying out for a solution. This collaboration will serve the industry by enabling a tightly integrated verification environment."

Initial members come from various quarters of the EDA industry. On the test bench side is Cadence Design Systems, Co-Design Automation, Forte Design Systems, and Verisity. Formal verification partners include Design Automation and Verplex Systems, while Innoveda covers hardware/software coverification. Debugging comes from Novas Software; memory modeling and verification from Denali Software; and resource management from Platform Computing.

As FastLink members, partners gain access to Axis' Xsim software simulator, which has a direct connection to Axis' RCC engine. Axis provides a software simulator that is directly linked to its hardware engines. Xsim makes it easy to integrate, test, and enhance the interoperability of Axis tools and verify that third party tools work properly with Axis' RCC engines.

Other key benefits of the program include joint marketing and integration development efforts. FastLink formalizes these efforts with third parties, providing them with software licenses, documentation, support, and software updates.

FastLink members' customers are primarily companies designing and developing SoCs for networking, communications, consumer, and computing applications. Verifying these complex SoCs requires many different tools that run simultaneously and communicate among various processes. Through FastLink, SoC designers gain assurance that their verification tools will operate effectively and that they have the vendors' support behind an integrated solution.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.