Zero-Delay Clock Buffers Tout Low Skew

March 1, 2001

Five new zero-delay buffers have been developed that meet the need for PC 133-compliant PLL buffers in applications requiring multiple low-skew clocks phase-matched to a reference clock. The devices meet JEDEC open standards, operate at 3.3V, and are spread-spectrum tolerant with a cycle-to-cycle jitter rate of ±75 ps.
The FS612509-01 with nine outputs and the FS612510-01 with 10 outputs operate at 133 MHz and are available in 24-pin TSSOPs. Having the same features, the FS612509-02 and FS612510-02 offer an auto power-down feature option that turns the PLL off and forces all outputs low when the reference clock stops. The FS6108 for PCI-bus applications is optimized for use at 33 MHz with a maximum output of 66 MHz and is available in a 16-pin SOIC package. Pricing is from $1.09 each/10,000.

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!