Tool Partitions And Prototypes ASICs And SOCs From RTL Code

Improved productivity for ASIC and SOC verification, including new pin-assignment capabilities, a new user interface, and partitioning aids are all features of Certify 2.1. The register-transfer-level partitioning and prototyping tool also includes support for Altera’s APEX and Xilinx’s Virtex PLDs.The tool addresses the increasing complexity of ASIC and SOC designs by simplifying PLD-based prototyping. It enables users to partition and synthesize complex RTL designs across multiple PLDs. New features in version 2.1 include a user interface that’s optimized for handling SOC designs by providing detailed feedback on black-box timing models used for non-synthesizable components. Also, the tool’s new partitioning aids include decomposition of large MUXs, bit-slicing of large primitives, and the ability to "zipper" functional blocks based on inputs or outputs.