EDA Update: Physical Synthesis For NEC's ISSP Architecture

Dec. 4, 2003

Physical synthesis for NEC's ISSP architecture is part of an expanded development and marketing deal between NEC and Synplicity Inc. The two will work to develop the Amplify ISSP Physical Optimizer, a physical synthesis tool for NEC's Instant Silicon Solution Platform structured ASICs. For further information, go to www.synplicity.com and www.nec.com.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.