Delay Line Enables Timing Adjustments

Sept. 1, 2000

The DS1100 5-tap, solid-state delay line is claimed to enable the extremely precise timing adjustments critical to optimum system operation. The chip's new architecture is said to minimize costs, power consumption, and package size. Timing delays for the device are trimmed to specification as individual delay elements. Settings are then stored in an EEPROM array after the die is packaged. Delay times range from 4 ns 300 ns. The DS1100 is available in a 5-V version, and a 3-V version is currently under development. Package options include an eight-pin DIP, SOP or SOIC. Another stated feature of the delay line is improved performance over temperature and voltage compared to older technologies. Pricing for the 5-V version is $1.93 each/1,000.

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