RTL Synthesis For SoCs Optimized For Large Designs

June 10, 2002

Offering a fast, high-capacity alternative for register-transfer level (RTL) synthesis of very large ICs, the RTL Compiler is optimized for design larger than 1 million gates with aggressive clock speeds. Built to be compatible with customer-owned tooling (COT) design flows, RTL Compiler sports fast runtimes and brings to the party such features as test insertion and power optimization. New analytic technologies include a global-based optimization engine enabling linear behavior over design and library size; constraint-directed logic, power, and datapath optimization; and highly efficient data representation. The tool's total negative slack optimization increases timing margins to optimize more than a design's critical paths, providing extra timing margin for near-critical nets. The tool is shipping now with a base price of $100,000.

Get2Chip Inc.
www.get2chip.com; (408) 501-9600

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.