SystemC Anchors IC Implementation Flow

The promise of SystemC, a design language that has often been touted as an answer to the burgeoning complexity of systems-on-a-chip (SoCs), is only as good as the path from algorithm to tapeout. CoWare and Forte Design are doing their part to fulfill the promise by forging tight links between CoWare's ConvergenSC SystemC-based SoC design tools and Forte's Cynthesizer, a SystemC behavioral synthesis tool.

The tight integration between the tools lets users explore and validate a design's system architecture in ConvergenSC and then synthesize to RTL using Cynthesizer. The RTL subsequently can be verified in a system context with the same SystemC model.

Any automated path from architectural-level SystemC models to RTL must avoid manual rework. It also must prevent divergence between the SystemC representation of the design and the resulting RTL representation. In the CoWare-Forte flow, users can automatically generate RTL for targeted subsystem blocks using Cynthesizer. Then they validate candidate RTL implementations in the system with embedded software.

Adopters of SystemC behavioral synthesis must have simulation to functionally verify their designs before and after synthesis. The integration of the two tools gives Cynthesizer users access to simulation with multithreaded SystemC debugging and SystemC/HDL cosimulation.

Both ConvergenSC and Cynthesizer are available now.