Typically, the inevitable boost in speed lures designers into levels of abstraction above RTL. The more abstract your design representation is, the faster it will simulate. Mentor Graphics' VStationTBX verification accelerator was updated to provide blinding speed for SystemC users. The tool now offers testbench acceleration for SystemC, generating verification results more than 500 times faster than co-simulation methods do.
Through its testbench compiler, VStationTBX compiles behavioral HDL with RTL, enabling designers to quickly map behavioral Verilog testbenches and memories into the VStationPRO emulator. In so doing, the tool eliminates the bottleneck and remodeling effort of cosimulation. It also provides automated support for transaction-based modeling methods and standard verification languages such as SystemC.
By combining the testbench compilation and transaction-based verification capabilities in the VStationTBX tool, designers can incrementally improve the effectiveness and reusability of their own testbenches.
Based on Mentor's TestBench Compiler, VStationTBX compiles two-state behavioral Verilog (including behavioral memory models) into the emulator for direct execution. The compiler provides an initial 20× to 200× performance boost for existing verification environments. Users then can migrate to higher levels of abstraction. This is done by linking C or hardware verification-language models to their design and testbench components in the emulator, ultimately achieving even higher performance.
Entry-level pricing for VStationTBX starts at $525,000. An entry-level configuration offers capacity from 1.6 million to 120 million gates and transaction-based verification at speeds from 300 to 600 kHz.
Mentor Graphicswww.mentor.com