Software Merges Design And Verification Tasks For ICs And IPs

Dec. 1, 1998

Developed to merge design and verification tasks for integrated circuits and semiconductor intellectual properties (IPs), SureSolve is an automatic functional verification package that generates Register Transfer Level (RTL) testbenches for earlier testing and verification of small blocks, as well as integrated system designs.The program is tightly integrated with firm's SureCov, a comprehensive coverage analysis software, to ensure a design is fully tested and verified. Together, the tools enable verification to start as soon as designers are coding at the RTL and automate recurring cycles in the design flow without changing the existing environment.SureSolve analyzes the flow of control and data through a Verilog RTL design and automatically builds a set of functional tests to completely exercise the design.

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