Breaking News: HDL Design And Simulation Environment

Feb. 2, 2004

Doubling the performance of the previous release, Version 6.2 of Active-HDL is an integrated, Windows-based HDL design and simulation environment. Behavioral, gate-level, and timing simulation performance benefit from up to a twofold speed boost for VHDL, Verilog, and mixed designs on all supported platforms. Other features include enhanced dataflow, library encryption, branch coverage, and X-trace. Pricing starts at $5900. Surf to www.aldec.com/ahdl for details.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.