Synthesis Environment Targets Deep-Submicron SoCs

March 4, 2002

A complete logic synthesis and timing environment is available to designers of deep-submicron SoCs in the form of Incentia Design Systems' DesignCraft. Incorporating the company's TimeCraft timing engine, it offers logic, datapath, test, and low-power...

David Maliniak

DesignCraft accepts design blocks three to five times larger than other logic synthesis tools. It also offers up to a tenfold runtime improvement with die size reductions of up to 20%.

Several patent-pending optimization techniques are provided, including register retiming. TimeCraft's timing engine, a full-chip, gate-level static timing analyzer for timing signoff, permits the use of the same set of complex timing constraints throughout the design, synthesis, and tapeout processes. It ensures a consistent timing result for timing closure.

DesignCraft is shipping now. It runs on Sun Solaris 32-bit and 64-bit HP-UX and Linux platforms. A time-based license starts at $33,000. The tool is compatible with flows from Synopsys, Cadence, and Avant!

Incentia Design Systems Inc., (408) 727-8988; www.incentia.com.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.