High Density 3.3V ISP PLDs Offer Speed

July 1, 1999

The ispLSI 2000VE family of 3.3V high-density programmable logic devices (PLDs) combines high performance and low voltage operation. The PLDs are based on the advanced architecture of firm’s SuperFAST ispLSI 2000E CPLDs and ispLSI 5000V SuperWIDE family of 3.3V devices to provide the broadest range of advanced ISP low-voltage logic devices ranging from 32 to 512 macrocells. The first two families are the 32-macrocell ispLSI 2032VE with 4-ns/200-MHz performance and the 128-macrocell ispLSI 2128VE with 5-ns/180-MHz speed. The ispLSI 2000VE devices are said to offer the fastest registered I/O timings of any 3.3V CPLDs with input-to-clock setup times of 2.5 ns and clock-to-output delays of 3 ns. All have 5V-tolerant I/O pins to support design migration from 5V to 3.3V.

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