Symbolic Simulation Products Tackle Functional Verification

Jan. 10, 2000
A pair of symbolic simulation products, the ESP-XV and the ESP-CV, can be used to address the problem of functional verification. Coverage can be improved, while the number of required simulation cycles is reducible. At the same time, they can fit...

A pair of symbolic simulation products, the ESP-XV and the ESP-CV, can be used to address the problem of functional verification. Coverage can be improved, while the number of required simulation cycles is reducible. At the same time, they can fit almost seamlessly into existing design environments. These Verilog-language symbolic simulators also accept symbols or variables, as well as 0/1/X/Z while carrying the variables through simulation as Boolean expressions. Consequently, one symbolic simulation can equal billions of today's simulation cycles.

The -XV model, intended for functional verification of language-based designs, lets users inject symbols into behavioral, RT, and gate-level blocks. Its concept of symbolic simulation includes "Symbolic Time," allowing users to inject an event at any and all times within a certain window. The -CV, meanwhile, is designed for custom and memory verification and sequential equivalence checking.

Supported on Sun and HP workstations, the list pricing for a floating license for these products starts at $100,000.

Innologic Systems Inc., 2860 Zanker Rd., Suite 203, San Jose, CA 95134; (408) 432-6188; e-mail: [email protected]; Internet: www.innologic-systems.com.

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