EDA Update: Design Exploration Tools

Sept. 29, 2003

New versions of Icinergy's design exploration tools introduce new capabilities for early physical planning of systems-on-a-chip (SoCs) and ASICs. SoC Preview ($9500) now can quickly generate .pdf datasheets for side-by-side comparison of alternative combinations of intellectual-property blocks, macros, and process technologies. SoC Plan ($20,000) includes interactive floorplanning, I/O placement, and interconnect planning facilities. SoC Prototype ($35,000) adds timing-driven block placement and automatic generation of synthesis constraints. Visit www.icinergy.com.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.