SoC Design Tool Performs Routing, Physical Optimization

March 4, 2002

NanoRoute-SI is a system-on-a-chip (SoC) design tool that concurrently performs timing-driven, noise-prevention routing, RC extraction, timing and noise analysis, buffer insertion, gate sizing, and logic restructuring as well as incremental placement within a single product. It incorporates the same graph-based routing engine as the firm's NanoRoute SoC router, combining the flexibilities equal to those of gridless routers and speed and capacity superior to grid-based routers.

A placed-design-to-GDSII capability complements existing design planning and physical-synthesis tools, eliminating costly design iterations. There's also support for physical design data, design constraints, and timing libraries in standard formats such as LEF/DEF, SDC, .lib, SDF, and GDSII, allowing easy adoption and integration into popular design flows with minimal adoption costs and learning curve.

NanoRoute-SI is available immediately. Pricing for a single-CPU configuration of NanoRoute-SI starts at $180,000 for a one-year, time-based subscription license.

Plato Design Systems Inc.
(408) 436-8612; www.platodesign.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.