Hot Product

March 31, 2003

Starting life as a design services organization, ReShape Inc. has brought its secret sauce to market in the form of the GDS Builder tool. This hierarchical physical design system coaxes the tools within an existing back-end physical flow to take a design from netlist to verified GDSII in two weeks or less, with layout quality akin to that derived using flat methodologies. Design respins can take less than 24 hours with remarkably repeatable results.

GDS Builder leans on two key elements to deliver such fast turnarounds. First, it constructs chips hierarchically, partitioning the design into blocks that can be built in parallel on fast, low-cost Linux servers. Second, it speeds up the verification process by bottling expertise in driving the user's existing analysis tools.

The tool's hierarchical approach generates extremely dense layouts that hinge on channel-less block abutment. The company's Design Aware technology automatically optimizes difficult tasks for hierarchical flows, including block pin assignment, global repeater insertion, and power distribution. It uses a given chip's previous builds as the basis for optimizations, exploiting design iteration.

GDS Builder supports Synopsys, Mentor Graphics, and Cadence tools. Call ReShape for pricing.

ReShape Inc.
www.reshape.com
(650) 230-3200

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.