Promising improved productivity for designers of current and future SoCs is Plato Design Systems' NanoRoute, a next-generation scalable router. According to the company, this tool is based on the industry's first graph-based routing technology. It also delivers more than 10 times the speedup and capacity improvements of the fastest grid-based routers.
Crosstalk and capacitive coupling between adjacent circuit traces are the bane of SoCs and other extremely dense ICs at submicron levels. With process technologies moving into the 0.18-µm region and below, designers are finding that timing and noise estimations made at the placement stage are inadequate, as they're typically only rough estimates of wire lengths. Without actually having routed the nets, it's nearly impossible to extract the parasitics that would indicate true timing.
NanoRoute addresses this through use of concurrent data models, online 3D RC extraction, and incremental delay and timing analysis. By performing concurrent routing and interconnect optimization, the tool identifies and corrects timing and signal integrity problems before reaching the verification stage. So, iterations between physical design and verification are kept to a minimum.
The constraint-driven tool endeavors to meet the timing requirements specified by the user in routing an SoC. Its scalable nature also lets users extend its speed and performance advantages by running the application in parallel on multiple-CPU workstations. Designers can achieve up to 12 times the speedup on a 16-CPU machine.
NanoRoute is shipping now for Sun and HP Unix workstations and Linux PCs. Prices start at $300,000.
Plato Design Systems Inc., 1735 Technology Dr., Suite 820, San Jose, CA 95110; (408) 436-8612; www.platodesign.com.
